//#define LOGIO -1
#ifndef LOGIO
	#define OutPortB(Addr, Data) WRITE_PORT_UCHAR((PUCHAR)Addr, Data)
	#define InPortB(Addr) READ_PORT_UCHAR((PUCHAR)Addr)
	#define OutPort(Addr, Data) WRITE_PORT_USHORT((PUSHORT)Addr, Data)
	#define InPort(Addr) READ_PORT_USHORT((PUSHORT)Addr)
#else
	static void OutPortB(ULONG Addr, UCHAR Data)
	{
		DBGONLY(DbgPrint(KOH " - %04lX << %02lX\n", Addr, Data + 0L));
		WRITE_PORT_UCHAR((PUCHAR)Addr, Data);
	}
	static UCHAR InPortB(ULONG Addr)
	{
		ULONG Data;
		Data = READ_PORT_UCHAR((PUCHAR)Addr);
		DBGONLY(DbgPrint(KOH " - %04lX >> %02lX\n", Addr, Data));
		return (UCHAR)(Data);
	}
	static void OutPort(ULONG Addr, USHORT Data)
	{
		DBGONLY(DbgPrint(KOH " - %04lX << %04lX\n", Addr, Data + 0L));
		WRITE_PORT_USHORT((PUSHORT)Addr, Data);
	}
	static USHORT InPort(ULONG Addr)
	{
		ULONG Data;
		Data = READ_PORT_USHORT((PUSHORT)Addr);
		DBGONLY(DbgPrint(KOH " - %04lX >> %04lX\n", Addr, Data));
		return (USHORT)(Data);
	}
#endif




static void CtrMode(USHORT Addr, UCHAR Ctr, UCHAR Mode)
{
  UCHAR Ctrl;
  Ctrl = (Ctr << 6) | 0x30 | (Mode << 1);
  OutPortB(Addr + 0x14 + 3, Ctrl);
}

static void CtrLoad(USHORT Addr, UCHAR Ctr, USHORT Val)
{
  OutPortB(Addr + 0x14 + Ctr, Val & 0xFF);
  OutPortB(Addr + 0x14 + Ctr, (Val >> 8) & 0xFF);
}




static void StartConversion(ULONG Base)
{
	OutPortB(Base + 0, 0);
}

static BOOLEAN WaitForData(ULONG Base)
{
	BOOLEAN Result;
	ULONG Timeout = 4; //~4 microsecond timeout
	while(TRUE)
	{
		if ((InPortB(Base + 8) & 0x80) == 0)
			return TRUE;
		if (--Timeout == 0)
			return FALSE;
	}
}

static USHORT ReadADData(ULONG Base)
{
	USHORT Result;
	Result = InPort(Base + 0);
	return Result;
}

static void EnableCTRAcq(USHORT Base)
{
	OutPortB(Base + 0x1D, 0x10);
	OutPortB(Base + 0x1E, 0xC0); //Enable counter-started conversions
	OutPortB(Base + 0x1B, 0x01); //Select counters 1 & 2 as counter trigger
	OutPortB(Base + 0x0C, 0x10); //Enable FIFO half IRQs
	CtrMode(Base, 0, 2);
	CtrMode(Base, 1, 2);
	CtrMode(Base, 2, 2);
	CtrLoad(Base, 0, 0x0005); //Ctr 0 determines between-channels timing
	OutPortB(Base + 0x01, 0x00); //Clear FIFO
	//Counters 1 and 2 need to be loaded and go needs to be issued
}

static void DisableCTRAcq(USHORT Base)
{
	OutPortB(Base + 0x0C, 0x00); //Disable FIFO half IRQs
	OutPortB(Base + 0x1E, 0x00); //Disable counter conversions
	OutPortB(Base + 0x1A, 0x22); //Stop card
}

static void ClearFIFO(ULONG Base)
{
	OutPortB(Base + 0x1, 0x00);
}